Espressif Systems /ESP32-P4 /AXI_DMA /IN_INT_ENA_CH1

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Interpret as IN_INT_ENA_CH1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_DONE_CH_INT_ENA)IN_DONE_CH_INT_ENA 0 (IN_SUC_EOF_CH_INT_ENA)IN_SUC_EOF_CH_INT_ENA 0 (IN_ERR_EOF_CH_INT_ENA)IN_ERR_EOF_CH_INT_ENA 0 (IN_DSCR_ERR_CH_INT_ENA)IN_DSCR_ERR_CH_INT_ENA 0 (IN_DSCR_EMPTY_CH_INT_ENA)IN_DSCR_EMPTY_CH_INT_ENA 0 (INFIFO_L1_OVF_CH_INT_ENA)INFIFO_L1_OVF_CH_INT_ENA 0 (INFIFO_L1_UDF_CH_INT_ENA)INFIFO_L1_UDF_CH_INT_ENA 0 (INFIFO_L2_OVF_CH_INT_ENA)INFIFO_L2_OVF_CH_INT_ENA 0 (INFIFO_L2_UDF_CH_INT_ENA)INFIFO_L2_UDF_CH_INT_ENA 0 (INFIFO_L3_OVF_CH_INT_ENA)INFIFO_L3_OVF_CH_INT_ENA 0 (INFIFO_L3_UDF_CH_INT_ENA)INFIFO_L3_UDF_CH_INT_ENA

Description

Interrupt enable bits of channel 0

Fields

IN_DONE_CH_INT_ENA

The interrupt enable bit for the IN_DONE_CH_INT interrupt.

IN_SUC_EOF_CH_INT_ENA

The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.

IN_ERR_EOF_CH_INT_ENA

The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.

IN_DSCR_ERR_CH_INT_ENA

The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.

IN_DSCR_EMPTY_CH_INT_ENA

The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.

INFIFO_L1_OVF_CH_INT_ENA

The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.

INFIFO_L1_UDF_CH_INT_ENA

The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.

INFIFO_L2_OVF_CH_INT_ENA

The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.

INFIFO_L2_UDF_CH_INT_ENA

The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.

INFIFO_L3_OVF_CH_INT_ENA

The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.

INFIFO_L3_UDF_CH_INT_ENA

The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.

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